1. Field of the Invention
This invention relates to integrated circuits and more particularly to clock generator integrated circuits.
2. Description of the Related Art
High speed communication systems require high speed clock signals for transmission and reception of information. In a typical clock generation circuit, a phase-locked loop (PLL) receives a synchronization input reference clock signal and generates one or more high speed clock signals suitable for use in transmitting or receiving data. According to one aspect of such a communication system, when the synchronization input reference clock signal is lost, the system enters a mode known as “holdover” mode and continues to output a clock signal.
The accuracy with which the clock generation circuit provides the clock signal in holdover mode is typically specified in a system standard. The clock generation circuit tries to maintain the output clock signal during holdover mode at a frequency based on a previous reference clock signal. While generating the clock signal in holdover mode, the PLL typically no longer uses feedback to generate the output clock signal. However, the frequency of the clock signal generated in holdover mode may still drift to such an extent as to fail to meet the holdover requirements. For example, certain PLLs may fail to meet holdover requirements because the voltage controlled oscillators utilized in such systems have too much frequency variation over temperature (e.g., 100 ppm/° C.).
Thus techniques that improve an integrated circuit implementation of clock signals generated in a holdover mode that achieves specifications for a high accuracy of the frequency of the output clock signal and low-jitter are desired.